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Apple supplier TSMC is making strides to improve its production capacity for chips based on its cutting-edge 3-nanometer process technology, according to industry sources, which is expected to debut in this year's iPhone 15 Pro and upcoming MacBook models.

tsmc_semiconductor_chip_inspection_678x452.jpg

DigiTimes reports that TSMC's 5nm fabrication capacity began to loosen in November 2022 as a result of reduced orders from Apple, amongst other partners, with orders for iPhone chips alone having been slashed by 30%. However, the Taiwanese manufacturer has apparently been able to keep its utilization rate at 70% or higher thanks to Apple's thirst for 3nm:
TSMC continues to improve its capacity utilization for 3nm process technology, which is expected to approach 50% at the end of March, the sources said. The foundry will also grow the process output to 50,000-55,000 wafers monthly in March, with Apple being the main customer.
Apple's upcoming iPhone 15 Pro models are expected to feature the A17 Bionic processor, Apple's first iPhone chip based on TSMC's first-generation 3nm process, also known as N3E.

The first-gen 3nm process is said to deliver a 35% power efficiency improvement over TSMC's 5nm-based N4 fabrication process, which was used to make the A16 Bionic chip for the iPhone 14 Pro and Pro Max. The N3 technology will also offer significantly improved performance compared to current chips manufactured on 5nm.

Apple's next-generation 13-inch and 15-inch MacBook Air models are both expected to be equipped with an M3 chip, which is also likely to be manufactured on the 3nm process for further performance and power efficiency improvements. Apple is also reportedly planning to release an updated version of the 13-inch MacBook Pro with an M3 chip. The M2 chip and its higher-end Pro and Max variants are built on TSMC's second-generation 5nm process.

Orders for new AI processors from Nvidia and AMD, as well as Apple's new iPhone chip, are expected to help TSMC avoid further fab utilization declines in the second quarter, DigiTimes' sources said.

Article Link: Apple's Huge 3nm Chip Orders for iPhone 15 Pro and M3 Macs Helping to Maintain TSMC's Fab Utilization Rates
 

Wxchaser

macrumors P6
Oct 28, 2017
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"Rapid slowdown in 7nm and 6nm chip orders, but the foundry has managed to keep its overall fab utilization rates at 70% or higher".
 

ian87w

macrumors G3
Feb 22, 2020
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Apple’s orders are so huge that it can literally make and break companies. Good ending ones include Corning, while bad ending ones include that company with sapphire glass.
 
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User 6502

macrumors 65816
Mar 6, 2014
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No surprise apple is going all-in on N3 given lackluster 14 sales. I skipped 14 for the incremental nature of the update.
Same here. I generally update every year but I skipped iPhone 14 because it was essentially an iPhone 13 rebranded and with increased price.
 
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applesed

macrumors 6502a
Jun 25, 2012
533
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Does anyone else see what’s happening here? Eventually the nm will require floating point numbers, and these devices will be in more everyday devices running chatGPT 10.0 and replace us (although I think 100-200 year timeline on that last part, if not 5000).
 
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jdb8167

macrumors 601
Nov 17, 2008
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Does anyone else see what’s happening here? Eventually the nm will require floating point numbers, and these devices will be in more everyday devices running chatGPT 10.0 and replace us (although I think 100-200 year timeline on that last part, if not 5000).
The industry is moving from nm to Ångströms. The node after 2 nm will be 18 å for example.
 

User 6502

macrumors 65816
Mar 6, 2014
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3 nanometer circuits... I still find this amazing. The first processor I ever experimented with was at 3500 nm. Not a typo.
it doesn’t seem real because it isn’t. The whole nm thing largely lost meaning and it has little to do with the actual transistor size. Sure there has been huge progress and they can squeeze so many more transistors in the same area than they used to, but 3nm is a misleading number. The truth is that we got to the limit of what’s physically possible: silicon atoms have a size and you can’t change that fact no matter how much research you do.
 

Aston441

macrumors 68030
Sep 16, 2014
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it doesn’t seem real because it isn’t. The whole nm thing largely lost meaning and it has little to do with the actual transistor size. Sure there has been huge progress and they can squeeze so many more transistors in the same area than they used to, but 3nm is a misleading number. The truth is that we got to the limit of what’s physically possible: silicon atoms have a size and you can’t change that fact no matter how much research you do.
What is the actual transistor size? I haven't been following that closely these past few years.
 

Aston441

macrumors 68030
Sep 16, 2014
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Well, looks like we could get 3nm devices for the next generation of devices indeed.
Now if Apple could also secure some of the production capacity from the currently declining memory market and bump up the capacities in the base models, that would make those devices a nicely rounded package.
HaHaHaHaHAHAHA 😂 you make funny joke
 

jdb8167

macrumors 601
Nov 17, 2008
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What is the actual transistor size? I haven't been following that closely these past few years.
From Wikipedia:
The term "5 nm" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors being 5 nanometers in size. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a "5 nm node is expected to have a contacted gate pitch of 51 nanometers and a tightest metal pitch of 30 nanometers".[3] However, in real world commercial practice, "5 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption compared to the previous 7 nm process.


The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systemspublished by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.[14]However, in real world commercial practice, "3 nm" is used primarily as a marketing term by individual microchip manufacturers to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[15][16] Moreover, there is no industry-wide agreement among different manufacturers about what numbers would define a 3 nm node. Typically the chip manufacturer refers to its own previous process node (in this case the 5 nm processnode) for comparison. For example, TSMC has stated that its 3 nm FinFET chips will reduce power consumption by 25-30% at the same speed, increase speed by 10-15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips.[17][18] On the other hand, Samsung has stated that its 3 nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process.

 
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giggles

macrumors 65816
Dec 15, 2012
1,049
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50-55k 3nm wafers in March…I think that would translate to around 18M M3 chips…potentially enough for every M3 Macbook Air 13”/15” and M3 iMac that will be sold in 2023…I wonder (I have no idea) if TSMC/Apple are building all the M3 chips first and then around May/June they will switch the full 3nm capacity to the A17..
 

jdb8167

macrumors 601
Nov 17, 2008
4,788
4,517
Holy crap! It's marketing BS 😂

I thought something was off. Years ago I remember reading that below 5nm might be impossible due to quantum effects / hard physical reality.

Obviously marketing doesn't have those limitations.
It’s marketing of the nm designation but the chips are still getting denser. The actual feature sizes isn’t what is causing the increased density. There are a bunch of other tricks like the upcoming GAA (gate all around) that exploit more of the 3D nature to get higher component density.
 
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